Read claim 1 before reading the title. US20260203368A1, published July 16, 2026 and assigned to Microsoft Technology Licensing, LLC, carries the title Methods for Lookup Table-Based Mixed-Precision Matrix Multiplication — but the title is not the scope. What the application actually claims is a specific four-step arithmetic substitution, and the claim recites it in order. The record is classified under CPC G06F 17/16 (matrix computation) and G06F 1/03 (digital function generation using tables), a pairing that describes the invention more honestly than the title does: this is matrix math done as table lookup. The named inventors are Mao Yang, Shijie Cao, Ting Cao, and Lingxiao Ma. The record contains 20 claims, three of them independent — 1, 10, and 18. This is a published application bearing kind code A1. It is pending. Nothing here has been granted, allowed, or examined to a conclusion that the public record before us reflects.

Claim 1 is a method claim, and its four moves are the whole idea. First, decompose: an n-bit weight matrix becomes a series of n one-bit matrices, which converts one n-bit problem into n one-bit problems. Second, receive an m-bit activation matrix where m is greater than n — the precision mismatch that makes the multiplication "mixed-precision" in the first place. Third, generate a lookup table of partial matrix multiplication results built from permutations of groups of that activation matrix against the one-bit weight matrices. Fourth, and this is the step that does the work: for each bit of an input weight matrix having a depth of g bits, retrieve partial results from the table using g-bit groups of the weight matrix as indices, then aggregate what comes back into a final result. The weights stop being operands and become addresses. Here is the claim's own recitation of the first three steps:

decomposing an n-bit weight matrix into a series of n one-bit matrices; receiving an m-bit activation matrix, where m>n; generating a lookup table of partial matrix multiplication results based on permutations of groups of the m-bit activation matrix and the n one-bit matrices— Methods for Lookup Table-Based Mixed-Precision Matrix Multiplication, US20260203368A1

The claim does not say why any of this is worth doing, and that is normal — claims recite structure, not motivation. The description supplies the motivation: general-purpose CPUs have no native instruction for multiplying low-bit weights against higher-precision activations, so the conventional path is to dequantize the weights back up to a precision the hardware's multiply-accumulate units can handle. If the weights are only one bit wide, though, the set of possible products is small and finite, which is precisely the condition under which enumerating every answer in advance beats computing them on demand. Multiply-accumulate becomes lookup-and-add. The application's own worked example is modest and concrete: groups of four activations enumerate to a sixteen-entry table, so a single lookup stands in for a four-element dot product.

Where the claims put the table

The interesting prosecution detail is not in claim 1 — it is in claim 2. Dependent claim 2 adds a single limitation: that the lookup table is stored in a register of a central processing unit. That one clause is where the application's engineering argument lives. The description is candid that lookup-table approaches to mixed-precision matrix multiplication are not new, and candid about why earlier ones disappointed: on GPUs, according to the filing, the practical kernel performance came in worse than dequantization-based kernels, because the fixed architecture offered either too little storage for the tables or table access that was not fast enough. Read against that background, claim 2 is the response — put the table in the fastest memory on the machine, the register file itself, and do the lookups with SIMD shuffle instructions the CPU already has. The description names TBL on ARM and PSHUF on x86, and describes supporting techniques including a lookup-table-centric data layout, weight interleaving to avoid unpacking reorder costs, and table quantization with mirror consolidation to shrink the tables. The filing is transparent that the register-resident approach is not free: it describes a register-count comparison of 144 eight-bit registers for the lookup-table method against 104 for llama.cpp, a cost the described techniques then work to mitigate.

Independent claim 10 restates the method as a computing system. Independent claim 18 goes somewhere else entirely — it claims a computing system whose CPU includes a register and at least one LUT unit built on a bit-serial circuit architecture, comprising N×M multiplexing units. Its recitation is dimensioned: for an activation matrix A[M, K] and a weight matrix W[N, K], decompose the weights into N grouped binary weights of K bits each, tile an array of M tables in the register with each table holding a number of entries that scales as two raised to the group width, broadcast the grouped binary weights to M multiplexing units and each table entry to N multiplexing units, retrieve, and aggregate. Claim 18 is claimed subject matter, not described silicon; the multiplexing units exist in the application's recitation, and the public record here says nothing about whether any of it has been built.

The day's Microsoft cohort

Twelve Microsoft applications published July 16, seven of them AI- or inference-related, and the cluster reads as several distinct levers on the cost of running a model. US20260203643A1 is directed to converting an existing model into a mixture-of-experts in place, locating subnetworks and adding a router that scores on hidden state and subnetwork saliency. US20260203652A1 covers knowledge distillation using a hybrid contrastive loss combining forward and reverse KL terms across teacher and student samples; it shares four inventors with the in-place MoE application. Set beside the hero, that is compute less, activate less, and ship less — three approaches to the same expense. Whether Microsoft frames them that way is not something the filings say; it is a reading of the day's records. Elsewhere in the cohort, US20260204338A1 reaches into quantum-mechanical calculation of protein properties by splitting polypeptide sequences into overlapping three-amino-acid fragments, US20260203604A1 claims an asynchronous serving architecture that returns a cached item while a generative item is produced, and on the silicon side US20260203224A1 is directed to a snoop filter with a disaggregated vector table.

Two cautions on US20260203368A1 specifically. First, the record names T-MAC and llama.cpp — the description discusses integrating T-MAC into llama.cpp and a threadpool conflict with the TVM runtime — but that is implementation discussion inside a specification, not evidence of a shipped integration or a release. Second, and more usefully for anyone tempted to quantify this: the record carries no performance figures. No speedup, no latency, no throughput, no memory or power number appears in what published. The structural details are all there is, and the structural details are enough to read the scope. Published is not granted; claims narrow during prosecution routinely, and claims 1, 10, and 18 as they read today are where the application starts, not where it necessarily ends.