Here's what published — published is not granted. Application US20210019630A1, "Loss-Error-Aware Quantization of a Low-Bit Neural Network," published January 21, 2021, lists inventors Anbang Yao, Aojun Zhou, and colleagues, with CPC codes G06N 3/084 (training), G06N 3/0472, and vision matching G06K 9/6257/6262 — an Intel research filing.
The mechanism is loss-aware quantization. Quantization shrinks a network by representing weights and activations with fewer bits — say 4 or 8 instead of 32 — which slashes memory and speeds up arithmetic. The danger is accuracy loss when the coarse low-bit values can't capture what the model needs. "Loss-error-aware" means the quantization decisions are guided by their effect on the training loss, so the method spends precision where it matters and saves bits where it doesn't.
This is the same strategic territory as weight clustering and pruning: making models small and cheap enough to run efficiently, especially on edge and accelerator hardware. The fact that it's loss-aware is the differentiator — it's a smarter quantizer that doesn't treat all weights equally. For a silicon company, owning the algorithm that maps full-precision models onto low-bit hardware is owning a piece of the value chain.
Because this is a publication, the verb is "claims as filed." The allowed claims, if a grant issues, may be narrower than the application suggests, and there is nothing to enforce until then. The document's worth is as a signal of Intel's quantization research direction.
The takeaway: US20210019630A1 is a published marker in the model-efficiency arms race — a loss-aware low-bit quantization method from Intel — and a reminder to read the eventual allowed claims, not the application title, before assessing scope.