Here's what actually issued. On June 11, 2024, Intel Corporation was granted US12008067B2, "Sparse matrix multiplication acceleration mechanism," inventors including Subramaniam Maiyuran and Jorge Parra. The CPC codes are arithmetic-and-dataflow: G06F 17/16 (matrix operations), G06F 7/4876, G06F 9/3001, plus memory code G06F 13/1673.
The mechanism is exploiting zeros. Many of the matrices in modern neural networks are sparse — full of zero-valued weights or activations, often deliberately, through pruning. Multiplying by zero wastes time and energy. A sparse matrix-multiplication accelerator skips the zeros: it stores only the nonzero entries and routes the hardware to compute only the products that matter. Done right, that turns sparsity into real speedups instead of wasted cycles.
This is the natural next move after dense matrix-multiply hardware: once you've made the full computation fast, you attack the redundant part of it. For Intel, whose accelerators compete on throughput per watt, owning a sparse-multiply mechanism protects an efficiency lever that becomes more valuable as models get larger and sparser.
On scope: granted B2, enforceable, but the claims describe a specific sparse-multiplication acceleration mechanism. Sparsity and sparse linear algebra are broad, well-studied fields; what's fenced is Intel's particular hardware mechanism. The arithmetic CPCs and claim 1 set the boundary.
The takeaway: US12008067B2 pairs naturally with the dense matrix-multiply grants in the record — together they show the silicon vendors patenting both halves of the accelerator story: do the math fast, then skip the math you don't need.