Here's what actually issued. On June 11, 2024, Intel Corporation was granted US12008067B2, "Sparse matrix multiplication acceleration mechanism," inventors including Subramaniam Maiyuran and Jorge Parra. The CPC codes are arithmetic-and-dataflow: G06F 17/16 (matrix operations), G06F 7/4876, G06F 9/3001, plus memory code G06F 13/1673.

The mechanism is exploiting zeros. Many of the matrices in modern neural networks are sparse — full of zero-valued weights or activations, often deliberately, through pruning. Multiplying by zero wastes time and energy. A sparse matrix-multiplication accelerator skips the zeros: it stores only the nonzero entries and routes the hardware to compute only the products that matter. Done right, that turns sparsity into real speedups instead of wasted cycles.

“An apparatus to facilitate acceleration of matrix multiplication operations. The apparatus comprises a systolic array including matrix multiplication hardware to perform multiply-add operations on received matrix data comprising data from a plurality of input matrices and sparse matrix acceleration…”— U.S. Patent No. 12,008,067 source

The independent claim is hardware, and it names the parts. Claim 1 describes a "systolic multiplier" with "a first set of first in first out (FIFO) buffers" for the first input matrix, "a second set of FIFO buffers" for the second, "a plurality of processing elements (PEs)" that read from both buffer sets and perform multiply-add operations, and "a plurality of storage elements to locally store intermediate matrix multiplication values." A systolic array is the classic dense matrix-multiply engine — a grid of PEs through which operands stream in lockstep — so the claim starts from a conventional accelerator and then adds the sparse machinery on top: "sparse matrix acceleration circuitry to detect zero values in the matrix data and perform one or more optimizations on the matrix data to reduce the multiply-add operations."

The specific optimization the claim recites is the surprising part. Rather than (or in addition to) simply gating individual zero multiplies, claim 1 reduces work "including swapping rows with other rows in a sub-matrix for each of a plurality of sub-matrices of the first input matrix." The hardware physically rearranges rows. Claim 2 explains the goal of the swap: it swaps "a first row having the predetermined threshold zero values with a second row not having the predetermined threshold zero values to enable the first row to be adjacent to a third row having the predetermined threshold zero values." In plain terms, the circuitry clusters the mostly-zero rows together so they become adjacent. Once sparse rows are grouped, the accelerator can treat the dense rows and the sparse rows differently — skipping or compacting the block of sparse rows wholesale instead of discovering zeros one at a time. Claim 13 states the objective explicitly: swap rows "to achieve a maximum number of adjacent rows having a predetermined threshold zero values." This is a data-layout transform implemented in silicon, which is why a memory CPC (G06F 13/1673) rides alongside the arithmetic ones.

The dependent claims add the compression and correctness plumbing. Claim 3 adds "compression circuitry to compress the matrix data," and claim 4 defines that compression concretely: "generating packed matrix data by removing zero values from the matrix data and generating an indicator vector to identify the location of the zero values in the packed matrix data." That is a standard sparse encoding — pack the nonzeros, keep a bitmask/indicator of where the zeros were — and claim 5 has the sparse acceleration circuitry consume that compressed data and identify the zeros "based on the indicator vector." Because the hardware physically swapped rows, it must undo the rearrangement on the way out: claim 7 performs "a reverse swapping on an output matrix," restoring the original row order so the mathematical result is unchanged even though the computation order was permuted. Claims 8 through 10 add "row adjustments" — "shifting all non-zero values of a row having more than the predetermined number of zero values," or "combining adjacent rows having more than the predetermined number of zero values" — further packing sparse rows together to cut multiply-adds. Claim 16 restates the whole apparatus as "a graphics processing unit (GPU)," tying the mechanism directly to Intel's accelerator silicon.

This is the natural next move after dense matrix-multiply hardware: once you've made the full computation fast, you attack the redundant part of it — here by reordering and packing sparse rows so the systolic array stops grinding through zeros, then reverse-swapping to keep the answer correct. For Intel, whose accelerators compete on throughput per watt, owning a sparse-multiply mechanism with this row-swap-and-pack approach protects an efficiency lever that becomes more valuable as models get larger and sparser.

On scope: granted B2, enforceable, but the claims describe a specific sparse-multiplication mechanism — a systolic multiplier with FIFO buffers, sparse acceleration circuitry that detects zeros, row swapping to cluster sparse rows, indicator-vector compression, reverse swapping on output, and row-combining adjustments. Sparsity and sparse linear algebra are broad, well-studied fields; what is fenced is Intel's particular row-reordering hardware mechanism, not the general idea of skipping zeros. The arithmetic and memory CPCs and claim 1 set the boundary.

It is worth drawing out why row swapping, an unusual move for a multiply engine, is the clever part. A systolic array is rigid by design: operands march through a fixed grid of processing elements in lockstep, which is what makes it fast and power-efficient but also what makes it bad at handling scattered zeros, since a lone zero in a dense stream still consumes a cycle. The claims sidestep that rigidity not by redesigning the array but by reshaping the data fed into it. By swapping rows so that the mostly-zero rows become adjacent (claim 2) and maximizing the count of such adjacent sparse rows (claim 13), the circuitry converts scattered sparsity into structured sparsity — contiguous blocks the hardware can skip or compact wholesale rather than zero-by-zero. The indicator-vector compression of claim 4 then packs those nonzeros and records where the zeros were, and the row-combining of claim 10 fuses adjacent sparse rows to shave still more multiply-adds. The catch with permuting rows is correctness: reordering the input changes the arrangement of the output, so claim 7's "reverse swapping on an output matrix" undoes the permutation at the end, guaranteeing the final result is identical to the dense computation. That round trip — permute to expose structure, compute cheaply, permute back to restore order — is the disclosed mechanism, and it is what distinguishes this from generic "skip the zeros" hardware.

The takeaway: US12008067B2 pairs naturally with the dense matrix-multiply grants in the record — together they show the silicon vendors patenting both halves of the accelerator story: do the math fast on a systolic array, then physically reorder and pack the matrix so you skip the math you don't need.